1. Field
Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to a semiconductor device with extended bandwidth of input/output signals and a test method thereof.
2. Description of the Related Art
Semiconductor memory devices operate to use input/output (I/O) signals of wide bandwidths in order for performance improvement thereof. Therefore, the semiconductor memory devices are provided with an increasing number of I/O lines, which are referred to as multi channel wide I/O semiconductor memory devices. A multi channel wide I/O semiconductor memory device includes a plurality of memory unit blocks that can independently operate without mutual interference. The respective memory unit blocks are referred to as channels.
FIG. 1 is a block diagram illustrating the configuration of a conventional multi channel wide I/O semiconductor memory device.
For illustration purposes, FIG. 1 shows a multi channel wide I/O semiconductor memory device having four memory unit blocks.
Referring to FIG. 1, a multi channel wide I/O semiconductor memory device 100 includes first to fourth memory unit blocks 110, 120, 130, and 140.
The respective memory unit blocks 110, 120, 130, and 140 include core regions 112, 122, 132, and 142 having memory cell arrays, connection regions 116, 126, 136, and 146 for interface with external devices (not shown), and peripheral regions 114, 124, 134, and 144 having peripheral circuits serving as a medium between the core regions 112, 122, 132, and 142 and the connection regions 116, 126, 136 and 146. The external devices may include devices (e.g., memory modules) for transmitting/receiving data to/from the first to fourth memory unit blocks 110, 120, 130, and 140.
FIG. 2 is an internal configuration diagram explaining the connection of the peripheral regions 114, 124, 134, and 144 with the connection regions 116, 126, 136, and 146.
Since all of the peripheral regions 114, 124, 134, and 144 have the same configuration, FIG. 2 shows only the first peripheral region 114 and the first connection region 116 for convenience sake.
Referring to FIG. 2, the first connection region 116 includes a plurality of data pads DQ0 to DQK configured to receive data from an external device and output data to the external device. Bump pads may be used for the plurality of data pads DQ0 to DQK so as to minimize an area occupied by the pads.
The first peripheral region 114 includes a plurality of global input/output lines GIO<0>_CH0 to GIO<K>_CH0, a plurality of input/output circuits 114_1A to 114_K+1A, and a plurality of electrostatic discharge (ESD) protection circuits 114_1B to 114_K+1B. The plurality of global input/output lines GIO<0>_CH0 to GIO<K>_CH0 are provided in 1:1 correspondence with the plurality of data pads DQ0 to DQK. The plurality of input/output circuits 114_1A to 114_K+1A are configured to load data applied through the plurality of data pads DQ0 to DQK on the plurality of global input/output lines GIO<0>_CH0 to GIO<K>_CH0 and output data applied through the plurality of global input/output lines GIO<0>_CH0 to GIO<K>_CH0 to the plurality of data pads DQ0 to DQK. The plurality of ESD protection circuits 114_1A to 114_k+1A are provided between the plurality of input/output circuits 114_1A to 114_k+1A and the plurality of data pads DQ0 to DQK and configured to protect the plurality of input/output circuits 114_1A to 114_k+1A from ESD flowing through the plurality of data pads DQ0 to DQK.
FIG. 3 is a block diagram illustrating the internal configuration of the first input/output circuit 114_1A of FIG. 2.
Referring to FIG. 3, the first input/output circuit 114_1A includes a first input circuit 114_1A_1 and a first output circuit 114_1A_2. The first input circuit 114_1A_1 is configured to load data, which is applied from the first data pad DQ0 and passes through the first ESD protection circuit 114_1B, on the first global input/output line GIO<0>_CH0. The first output circuit 114_1A_2 is configured to output data applied from the first global input/output line GIO<0>_CH0 to the first data pad DQ0.
The first input circuit 114_1A_1 includes a first input buffer unit 114_1A_11, a first delay unit 114_1A_13, and a first line driving unit 114_1A_15. The first input buffer unit 114_1A_11 is configured to buffer data applied from the first data pad DQ0. The first delay unit 114_1A_13 is configured to delay the data buffered by the first input buffer unit 114_1A_11 by a predetermined time. The first line driving unit 114_1A_15 is configured to drive potential/voltage to the first global input/output line GIO<0>_CH0 in response to the output signal of the first delay unit 114_1A_13. The first delay unit 114_1A_13 performs a delay operation based on a setup time and a hold time.
The first output circuit 114_1A_2 includes a first data alignment unit 114_1A_21, a first pre-driver 114_1A_23, and a first main driver 114_1A_25. The first data alignment unit 114_1A_21 is configured to align data loaded on the first global input/output line GIO<0>_CH0. The first pre-driver 114_1A_23 is configured to adjust a slew rate of data outputted from the first data alignment unit 114_1A_21. The first main driver 114_1A_25 is configured to adjust driving power of data outputted from the first pre-driver 114_1A_23.
In the conventional multi channel wide I/O semiconductor memory device 100, the first to fourth memory unit blocks 110, 120, 130, and 140 may perform data input/output operations independently without mutual influence and input/output data at wide bandwidth.
However, the conventional multi channel wide I/O semiconductor memory device 100 may use bump pads as the plurality of data pads DQ0 to DQK as described above. Since the bump pads are small in size than general data pads, it may be difficult to use the semiconductor memory device in the existing test environment. That is, since the bump pads are small in size, the multi channel wide I/O semiconductor memory device 100 may not be tested using the existing test equipment. Moreover, the existing test equipment may not have a test environment for testing independent operations of the multi channel wide I/O semiconductor memory device 100.